Single and dual charge storage region NVM memory cells are known in the art. One such memory cell is the NROM (nitride read only memory) cell 10, shown in FIG. 1 to which reference is now made, which stores two bits 12 and 14 in a nitride based layer 16 sandwiched between a conductive layer 18 and a channel 20. NROM cells are described in many patents, for example in U.S. Pat. No. 6,649,972, assigned to the common assignees of the present invention, whose disclosure is incorporated herein.
Bits 12 and 14 are individually accessible, and thus, may be programmed (conventionally noted as a ‘0’), erased (conventionally noted as a ‘1’) or read separately. Reading a bit (12 or 14) involves determining if a threshold voltage Vt, as seen when reading the particular bit, is above (programmed) or below (erased) a read reference voltage level RD.
FIG. 2A, to which reference is now made, illustrates the distribution of programmed and erased states of a memory chip (which typically has a large multiplicity of NROM cells formed into a memory array) as a function of threshold voltage Vt. An erased bit is one whose threshold voltage has been reduced below an erase threshold voltage EV. Thus, an erase distribution 30 has typically its rightmost point in the vicinity of (and preferably at or below) the erase threshold voltage EV. Similarly, a programmed bit is one whose threshold voltage has been increased above a program threshold voltage PV. Thus, a programmed distribution 32 has typically its leftmost point in the vicinity of (and preferably at or above) the program threshold voltage PV.
The difference between the two threshold voltages PV and EV is a window W0 of operation. Read reference voltage level RD is typically placed within window W0 and can be generated, as an example, from a read reference cell. The read reference cell is usually, but not necessarily, in a non-native state, as described in U.S. Pat. No. 6,490,204, assigned to the common assignee of the present invention, whose disclosure is incorporated herein by reference. In such case, the threshold voltage of read reference cell may be at the RD level in FIG. 2A.
The signal from the bit being read is then compared with a comparison circuit (e.g. a differential sense amplifier) to the signal generated by the read reference level, and the result should determine if the array cell is in a programmed or erased state. Alternatively, instead of using a reference cell, the read reference signal can be an independently generated voltage or a current signal. Other methods to generate a read reference signal are known in the art.
Since the sensing scheme circuitry may not be perfect, and its characteristics may vary at different operating and environmental conditions, margins M0 and M1 are typically required to correctly read a ‘0’ and a ‘1’, respectively. As long as the programmed and erased distributions are beyond these margins, reliable reads may be achieved. However, the issue of maintaining a proper margin and reading memory cells become more complicated when dealing with multi-level-cells (“MLC”).
In a MLC, two or more programming levels may co-exist on the same cell, as is drawn in FIG. 2B. In the case where an MLC cell is being read to determine at which one of the multiple logical states the cell resides, at least two read reference cells must be used. During read operation, it must be determined that the MLC cell's threshold is in one of three or more regions bounded by the two or more threshold voltages defined by read reference cells. As is depicted in FIG. 2B, the voltage threshold boundaries which define a given state in an MLC are usually considerably smaller than those for a binary NVM cell. FIG. 2B, to which reference is now made, illustrates four different threshold voltage regions of an MLC, where each region is associated with either one of the programmed states of the MLC or with the erased state of the MLC. Because in an MLC a rather fixed range of potential threshold voltages (e.g. 3 Volts to 9 Volts) needs to be split into several sub-ranges or regions, the size of each sub-range or region in an MLC is usually smaller than a region of a binary NVM cell, which binary cell only requires two voltage threshold regions, as seen in FIG. 2A.
The voltage threshold of a NVM cell seldom stays fixed. Threshold voltage drift is a phenomenon which may result in large variations of the threshold voltage of a memory cell. These variations may occur due to charge leakage from the cell's charge storage region, temperature changes, and due to interference from the operation of neighboring NVM cells. FIG. 2C, to which reference is now made, shows a graph depicting threshold voltages (Vt) changes associated with two program states of an exemplary MLC due to drift, as a function of time, for 10 cycles and for 1000 cycles. As seen in the graph, voltage drift may occur across numerous cells, and may occur in a correlated pattern across these cells. It is also known that the magnitude and directions of the drifts depends upon the number of times the NVM went through program and erase cycles and on the level of programming of a MLC. It is also known that deviations in cells' (Vt) may be either in the upward or downward directions.
Variation of the threshold voltage of memory cells may lead to false reads of the state and may further result in the corruption of the data in the memory array. Voltage drift is especially problematic in MLC cells where the Vt regions or sub-ranges associated with each programmed state are relatively smaller than those for a typical binary cell.
In order to reduce data loss and data corruption due to drift in the threshold voltages of the cells of a NVM array, threshold voltage drift of cells in the NVM array should be compensated for. For a given NVM array, it would be desired to provide one or a set of reference cells whose references threshold voltages are offset from defined verify threshold levels by some value related to the actual voltage drift experienced by the NVM cells to be read. U.S. Pat. No. 6,992,932, assigned to the common assignee of the present application and incorporated herein by reference teaches some solutions to the above mentioned issues. However, there is a well understood and continuing need for more efficient and reliable methods of determining a set of reference voltage levels which may accommodate variations in the threshold voltages of cells of an NVM array, and of established reference cells with the determined reference voltages.